sampling clock造句
例句与造句
- Of course the sampling clock is itself a digital signal
时钟本身也是数字信号，也会干扰模拟电路。 - The sampling clock generator must also have adequate spectral purity
时钟发生电路固有的抖动应该足够小。 - Figure 5 . 36 shows the relationship between sampling clock jitter and snr previously presented
图5 . 36显示了采样时钟抖动和信噪比之间的关系。 - To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
为此，时钟信号应该尽可能地与电路中强噪声的部分隔离开，例如数字电路。 - The adc aperture jitter must be minimal , and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。 - It's difficult to find sampling clock in a sentence. 用sampling clock造句挺难的
- The ep2s15 of altera company , work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller
Altera公司的ep2s15作为系统的外围控制器,实现对系统的fifo (先进先出存储器)与采样时钟的控制。 - In this paper design of some circuit including in a / d circuit is also analyzed , such as front analog circuit , sample clock circuit and data flip - latch circuit
同时对高速转换器件及转换电路中包括前端模拟电路、采样时钟、后端数据锁存等辅助电路设计进行了分析。 - As to phased array receiving , a scheme of separating the delay clock and sampling clock is explicated , which effectively enhance the phased receiving delay resolution
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。 - Those include power supply circuit design ; ground plane design and sample clock design . combining some radar development , its high - speed a / d circuit is tested , and has given out some test results
最后结合某雷达研制，对其高速模数转换电路设计进行了实际测试评估，并给出了部分测试结果。 - Such as harmonic distorted in front analog circuit , sample clock shaking , analog power and the noise in ground plane etc . some suggestion of circuit design is given to improve high - speed a / d circuit performance
在高速模数转换电路的应用设计中地电源供电设计、模数地平面设计、采样时钟设计等方面提出一些具有指导性的意见。 - The effects of sampling clock jitter on signal - to - noise ratio ( snr ) and effective bit ( enob ) performance discussed in section 3 are even more dramatic in undersampling applications because of the higher input signal frequencies
在第三章讨论的采样时钟抖动对信噪比和有效位性能的影响在欠采样应用中因为更高的输入信号频率显得更有戏剧性。 - The functional module and the mainboard compose an automatic measurement instrumentation with real - time data acquisition and processing function . this module involves two multi - channel adc and the sample clock is shared between these adc so as to synchronization
本模块使用了单片集成多通道同步a d转换器，并在转换器之间共享采样时钟的方法在模块内部实现了通道间同步。 - The fpga of xilinx inc . works as a important part , with which many functional modules , including a controller of lcd display , a fifo ( first in first out ) memory , a controller of sampling clock , and so on , were implemented
Xilinx公司的fpga （现场可编程门阵列）作为系统的外围控制器，实现系统的其他很多功能模块，包括lcd （液晶显示）控制器、测频和测周模块、 fifo （先进现出存储器） 、采样时钟控制器，等等。 - It was satisfied for performance testing of high - speed a / d circuit in the project assess the factors of reducing a high speed a / d circuit performance were found out , such as harmonic distorted in front analog circuit , . sample clock shaking , analog power and the noise in ground plane etc
并在试验测试的基础上找出了影响高速模数转换电路转换性能的几个主要的因素，即：前端运放电路谐波失真、采样时钟抖动、模数电源及共地噪声串扰等。 - In particular , buffers used for the sampling clock should , ideally , be on separate chips , with separately decoupled supplies , from the remainder of the digital system , and the sampling clock signal lines should not be sited where they can pick up digital noise from the rest of the system
特别要注意的是， （理想地， ）时钟的缓冲器应该由独立的芯片构成，缓冲器不能与噪声部分共用电源，电源要良好去耦，而且信号线的布线方式不能引入噪声。
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